This invention relates to a clock control circuit which generates various internal clocks that have specific phase relationships with an external clock.
In semiconductor systems, including a synchronous DRAM (SDRAM), to fetch the data read from a memory surely outside the memory, it is necessary to set a time interval called a data window and output the data within the data window. To set such a data window, it is necessary to generate an internal clock having a specific phase relationship with an external clock. To achieve this, a clock control circuit is used.
A conventional clock control circuit, however, has the problem that it does not operate properly when the cycle time of an external clock is short.